SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.
| RXRDYEN | Writing 1 clears the corresponding bits in the INTENSET register. |
| TXRDYEN | Writing 1 clears the corresponding bits in the INTENSET register. |
| RXOVEN | Writing 1 clears the corresponding bits in the INTENSET register. |
| TXUREN | Writing 1 clears the corresponding bits in the INTENSET register. |
| SSAEN | Writing 1 clears the corresponding bits in the INTENSET register. |
| SSDEN | Writing 1 clears the corresponding bits in the INTENSET register. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| MSTIDLE | Writing 1 clears the corresponding bits in the MSTIDLE register. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |